The present invention relates to an active matrix liquid crystal display device made up of an active matrix array provided with switching elements at each intersection between a plurality of scanning lines and a plurality of signal lines, a vertical drive circuit for driving the scanning lines, and a horizontal drive circuit for driving the signal lines; and to a method of driving such a liquid crystal display device.
Recent years have seen increasing demand for liquid crystal display devices which are compatible with personal computers or work stations, televisions, etc. having different video frequencies, numbers of pixels, and scanning methods.
In order for a single liquid crystal display device to achieve compatibility with a variety of sources such as the foregoing personal computers or workstations, televisions, etc., the liquid crystal display device must perform a variety of scanning methods, such as interlace driving, two-line simultaneous driving, non-interlace driving, etc., as will be explained below.
For compatibility with the foregoing personal computers or workstations, sequential scanning must be performed, in which lines are scanned sequentially, regardless of whether they are odd-numbered or even-numbered lines. For compatibility with existing televisions or hi-vision televisions, on the other hand, interlace scanning must be performed, in which the pixels of odd-numbered lines are sequentially scanned during an odd-number field, and the pixels of even-numbered lines are sequentially scanned during an even-number field.
Further, there are also cases when two-line simultaneous scanning is performed, in which, when scanning an odd-numbered line during the odd-number field, the next even-numbered line is also scanned and the same signal is written therein, and when scanning an even-numbered line during the even-number field, the next odd-numbered line is also scanned and the same signal is written therein. Thus liquid crystal display devices compatible with this scanning method are also called for.
Further, liquid crystal display devices are called for which are capable of each of the foregoing scanning methods, and also of enlarged display, movement, black display writing, bi-directional scanning, etc.
Again, with the aim of reducing the size and cost of liquid crystal display devices, research is also in progress to develop techniques for integrating peripheral drive circuits onto the same substrate with the liquid crystal display device. Peripheral drive circuits are divided into a vertical drive circuit, which scans the gates of thin film transistors (TFTs) making up an active matrix array, and a horizontal drive circuit, which supplies video signals to pixels.
This type of liquid crystal display device is disclosed in, for example, Japanese Unexamined Patent Publication No. 8-122747/1996 (Tokukaihei 8-122747). The following will explain this conventional liquid crystal display device.
The foregoing conventional liquid crystal display device, as shown in FIG. 31, includes an active matrix array 201 made up of TFTs, one provided at each intersection between scanning lines and signal lines, a vertical drive circuit 202 for driving the scanning lines, and a horizontal drive circuit 203 for driving the signal lines. In this conventional liquid crystal display device, there are 1,024 scanning lines.
In the foregoing conventional liquid crystal display device, as shown in the Figure, the vertical drive circuit 202 is made up of 256 scanning circuits 204-1 through 204-257 having a half-bit structure (hereinafter referred to as xe2x80x9chalf-bit scanning circuitsxe2x80x9d), which sequentially shift a pulse signal inputted from an input terminal a or an input terminal b in synchronization with a clock signal; NAND gate circuits 205-1 through 205-1024, which receive signals P1, P2, . . . , P256 outputted by the half-bit scanning circuits 204-1 through 204-257 and control signals G1, G2, . . . , G8; and output buffers 206, which receive signals outputted by the NAND gate circuits 205-1 through 205-1024.
In the foregoing conventional liquid crystal display device, four NAND gate circuits 205 are connected to each half-bit scanning circuit 204-1 through 204-257, and every eight adjacent NAND gate circuits 205 receive different respective control signals G1 through G8.
Further, each of the half-bit scanning circuits 204-1 through 204-257 is capable of bi-directional scanning. Accordingly, a pulse signal is inputted from the input terminal a when scanning in one direction, and from the input terminal b when scanning in the other direction.
The half-bit scanning circuits 204-1 through 204-257 are circuits driven by two clock signals of different respective phase. Consequently, the number of driving signals necessary to drive the half-bit scanning circuits 204-1 through 204-257, including the pulse signal inputted when scanning in the other direction, are two clock signals and two input signals, or a total of four signals. Further, when the control signals G1 through G8 for the NAND gate circuits 205-1 through 205-1024 are included, the total number of driving signals inputted to the vertical drive circuit 202 is 12 signals. This number of signals does not change even when the number of scanning lines exceeds 1,024.
FIG. 32 shows one example of a driving method for the conventional liquid crystal display device shown in FIG. 31. The following will explain, with reference to FIG. 32, a method of driving the conventional liquid crystal display device shown in FIG. 31.
First, as shown in FIG. 32, a clock signal CLK having a clock cycle of 8T (T being a scanning line selection period) and an input pulse signal VSTa from the input terminal a having a pulse width of 8T are sent to the half-bit scanning circuits 204-1 through 204-257 with the timings shown in the Figure, and thus the input pulse signal VSTa is sequentially shifted in synchronization with the clock signal CLK.
Consequently, the signals P1 through P256 outputted by the respective half-bit scanning circuits 204-1 through 204-257, as shown in the Figure, are pulse signals having a pulse width of 8T and phases sequentially shifted 4T each.
Meanwhile, as the control signals G1 through G8, pulse signals having a pulse width of T, a pulse cycle of 8T, and phases sequentially shifted T each are sent to the NAND gate circuits 205-1 through 205-1024 with the timings shown in the Figure. As a result, signals GP1 through GP1024 outputted by the respective output buffer circuits 206 are pulse signals having a pulse width of T and phases sequentially shifted T each.
The foregoing driving method explains signals used in sequential scanning.
Further, there is also a demand for liquid crystal display devices which are freely capable of enlarged display of images having fewer pixels than the liquid crystal display device. Such liquid crystal display devices are usually realized by modifying the structure of the vertical drive circuit or the driving method.
Further, when displaying an image having fewer pixels than the liquid crystal display device, in order to show black display in unused areas above, below, to the right, and to the left of the area used for liquid crystal display, it is necessary to perform writing of black display to the pixels of the unused areas during a blanking period.
Further, in liquid crystal projector devices, which in recent years are seeing increased use as large-screen displays, presentation displays, etc., it is necessary for one of the three liquid crystal panels corresponding to R, G, and B to reverse its display using a mirror, because of differences in reflection of light transmitted through the liquid crystal display device and in the number of times the light is refracted. In addition, there is a demand for flexible liquid crystal display devices capable of both front and rear projection, and of both floor mounting and ceiling suspension. For these reasons, the scanning circuits provided in both the vertical and horizontal drive circuits must be capable of bi-directional scanning.
One example of a horizontal drive circuit in a conventional liquid crystal display device is the horizontal drive circuit in the liquid crystal display device disclosed in Japanese Unexamined Patent Publication No. 8-122748/1996 (Tokukaihei 8-122748).
The following will explain in detail specific examples of a liquid crystal display device and a driving method disclosed in the foregoing publication. As shown in FIG. 33, this conventional liquid crystal display device includes an active matrix array 301 made up of TFTs provided at each intersection between scanning lines and signal lines, a vertical drive circuit 302 for driving the scanning lines, and a horizontal drive circuit 303 for driving the signal lines. As shown in the Figure, the horizontal drive circuit 303 includes a horizontal scanning circuit 304 and sample holding switches 308, which are controlled by signals outputted by the horizontal scanning circuit 304. Here, control terminals of every 16 adjacent sample holding switches 308 are connected together, and input terminals of every 16th sample holding switch 308 are connected together. By inputting video signals S1 through S16, developed into 16 phases, to the input terminals of each group of 16 adjacent sample holding switches 308, 16 video signals are successively written via each group of 16 adjacent sample holding switches 308 selected in succession. Sample holding capacitances 309 hold a video signal written into a data bus line, and are holding capacitances for writing the held voltage into the pixels.
In this example of the foregoing conventional structure, there are 1,280 signal lines, and video signals developed into 16 phases are inputted. In this case, as shown in FIG. 33, a horizontal scanning circuit 304 of 80 bits is needed.
In the foregoing conventional liquid crystal display device, as shown in FIG. 33, the horizontal scanning circuit 304 is made up of 20 scanning circuits 305-1 through 305-21 having a half-bit structure (hereinafter referred to as xe2x80x9chalf-bit scanning circuitsxe2x80x9d), which sequentially shift a pulse signal inputted from an input terminal 310 in synchronization with a clock signal; NAND gate circuits 801-1 through 801-80, which receive signals P1, P2, . . . , P20 outputted by the half-bit scanning circuits 305-1 through 305-21 and control signals D1 through D8; and inverse output buffers 802-1 through 802-80, which receive signals outputted by the NAND gate circuits 801-1 through 801-80.
Four NAND gate circuits 801 are connected to and receive the output of each half-bit scanning circuit 305-1 through 305-21, and every eight adjacent NAND gate circuits 801 receive different respective control signals D1 through D8.
Further, each of the half-bit scanning circuits 305-1 through 305-21 is capable of bi-directional scanning. Accordingly, a pulse signal is inputted from the input terminal 310 when scanning in one direction, and from the input terminal 311 when scanning in the other direction.
The half-bit scanning circuits 305-1 through 305-21 are circuits driven by two clock signals of different respective phases. Accordingly, the number of driving signals necessary to drive the half-bit scanning circuits 305-1 through 305-21, including the pulse signal inputted when scanning in the other direction, are two clock signals and two input signals, or a total of four signals. Further, when the control signals D1 through D8 for the NAND gate circuits 801-1 through 801-80 are included, the total number of driving signals inputted to the horizontal scanning circuit 304 is 12 signals.
The foregoing conventional example is structured so that there are 20 half-bit scanning circuits, and so that the output of each half-bit scanning circuit is sent to four NAND gate circuits. However, it is also possible to use a structure of 10 half-bit scanning circuits, the output of each of which is sent to eight NAND gate circuits.
FIG. 34 shows a method of driving the foregoing conventional liquid crystal display device, showing one example of a driving method for writing video signals into data bus lines using the liquid crystal display device shown in FIG. 33. The following will explain this conventional driving method with reference to FIG. 34.
First, a clock signal CLK having a clock cycle of 8T (T being a sample holding switch sampling period) and an input pulse signal VSTa from the input terminal 310 having a pulse width of 8T are sent to the half-bit scanning circuits 305-1 through 305-21 with the timings shown in FIG. 34, and thus the input pulse signal VSTa is sequentially shifted in synchronization with the clock signal CLK. Consequently, signals P1 through P20 outputted by the respective half-bit scanning circuits 305-1 through 305-21, as shown in the Figure, are pulse signals having a pulse width of 8T and phases sequentially shifted 4T each. The scanning circuits are generally driven using two clock signals of different respective phases.
Meanwhile, as the control signals D1 through D8, pulse signals having a pulse width of T and a pulse cycle of 8T are sent to the NAND gate circuits 801-1 through 801-80 with the timings shown in the Figure. As a result, signals SP1 through SP80 outputted by the respective NAND gate circuits 801-1 through 801-80 are sampling pulses having a pulse width of T and phases sequentially shifted T each. The 16 adjacent sample holding switches 308 sampled by one of the sampling pulses SP1 through SP80 sample the 16 phases of parallel data signals S1 through S16 at the timings t1, t2, t3, . . . , t80, when the sampling pulse drops (as shown in the Figure), thus writing video signals into the data bus lines.
By means of the driving method explained above, the video signals can be written into the data bus lines.
In the foregoing conventional example, since each of the outputs P1 through P20 from the scanning circuits is sent to four NAND gate circuits, there are eight control signals, but if, for example, eight NAND gate circuits were connected to the output P1, 16 control signals would be necessary.
The more logic gate circuits connected to each output from the scanning circuits, the more control signals necessary. These control signals must be produced by an external circuit. With the foregoing conventional liquid crystal display device and driving method, among the driving signals inputted to the drive circuit, eight are control signals, and these control signals must be produced by an external circuit.
Further, each control signal requires one line for conducting the control signal from an input pad to the interior of the drive circuit. In the foregoing example, eight lines are required for conducting the control signals from the input pad to the interior of the drive circuit. Consequently, the surface area needed for these lines is increased, and since the input pad for input of the control signals is provided on the substrate, the surface area needed for the pad is also increased. Accordingly, the surface area of a glass substrate required for one liquid crystal device is increased, which reduces the number of liquid crystal panels which can be run from a common glass substrate.
Another problem is that increase in the number of input pads is one cause of reduced production efficiency when connecting the pads to an external flexible substrate.
It is an object of the present invention to provide a liquid crystal display device and a driving method therefor which use a small number of driving signals for operating the liquid crystal display device, and which are capable of improving production efficiency.
In order to attain the foregoing object, a liquid crystal display device according to the present invention includes an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, and driving means for driving the active matrix array, in which the driving means include:
scanning circuits N in number (N being a positive integer), which receive a start pulse, and which output respective pulse signals sequentially shifted by one-half of a clock signal cycle for each scanning circuit;
first logic gate circuits Nxc3x97M in number (M being an integer no less than 2), each provided with a first control terminal and a second control terminal, every M adjacent first logic gate circuits being connected together via the first control terminals thereof, which receive a signal from one of the N scanning circuits, and every Mth first logic gate circuit being connected together via the second control terminals thereof, which receive one of M kinds of second control signal;
second logic gate circuits, each of which receives an output from one of the first logic gate circuits and, via a third control terminal, one of two kinds of third control signal.
In the liquid crystal display device structured as above, the control signals inputted into the driving means are the start pulse and the clock signal inputted into the first of the N scanning circuits (N being a positive integer), the M kinds of second control signal inputted into the Nxc3x97M first logic gate circuits, and the two kinds of third control signal sent to the second logic gate circuits.
In the conventional structure, since a different kind of signal was sent to every 2Mth first logic gate circuit, at least 2M control lines were necessary for input to the first logic gate circuits. This increased the number of control lines for input to the driving means, which increased the surface area used for input pads, and since the control lines themselves had to be conducted to the driving means, the surface area devoted thereto in the circuit layout was also increased.
In contrast, with the liquid crystal display device according to the present invention, structured as above, the second control terminals of every Mth first logic gate circuit are connected together. For this reason, the number of second control signals required are M kinds, or half as many as conventionally.
Further, lines are dispersed between the first and second logic gate circuits, thus preventing concentration of control lines.
In other words, by reducing the number of control terminals, the surface area devoted to the drive circuit and to input pads can be reduced, and accordingly, when running a plurality of liquid crystal display devices from a common substrate, more elements can fit on one substrate, thus increasing the number of panels.
Further, since the surface area devoted to the drive circuit and input pads is reduced, the size of the peripheral area surrounding the display section of the liquid crystal display device is reduced, and installation in a personal computer, etc. is facilitated.
In addition, by increasing the number of outputs from each scanning circuit to the logic gate circuits so that the output of each scanning circuit is inputted into a plurality of logic gate circuits, the number of scanning circuits can be reduced. Particularly in high-definition liquid crystal display devices, layout of each scanning circuit within the small pixel pitch is difficult, but with the foregoing structure according to the present invention, layout can be simplified.
As a result, it is possible to provide a liquid crystal display device which is operated by a small number of driving signals, and which is capable of improving production efficiency.
The foregoing driving means may be a vertical drive circuit for driving the foregoing plurality of scanning lines.
Alternatively, the foregoing driving means may be a horizontal drive circuit, which may include sample holding switches.
The liquid crystal display device according to the present invention may be driven using sequential scanning, interlace scanning, or two-line simultaneous scanning.
Additional objects, features, and strengths of the present invention will be made clear by the description below. Further, the advantages of the present invention will be evident from the following explanation in reference to the drawings.